FIG. 1 is a block diagram of a serializer-deserializer (SERDES) 10. The SERDES 10 comprises a serializer 12 with a dedicated deserializer 14. The serializer 12 and deserializer 14 work together to achieve high bandwidth communication through stringent timing of components and reproducible signal positioning. In general, SERDES offer increased throughput by compressing numerous data inputs into differential pairs. A plurality of signals 16 enter the serializer “horizontally” and are “vertically” aligned such that in one clock period, one set of parallel bits (typically a single word of data) is transmitted serially over a pair of transmission lines 18. The deserializer 14 receives horizontally aligned signal and re-constitutes them horizontally onto parallel lines 20. The serializer 12 and the deserializer 14 typically communicate at gigabit speeds using differential signaling. There are many differential signaling standards such as ECL/PECL, LVDS, CML, and others.
Both the serializer 12 and the deserializer 14 operate using an internal frequency set using a clock signal. The transmit clock in the serializer 12 latches the data into the serializer 12 and is embedded in into the serial stream. At the other end, the deserializer 14 recovers the embedded clock with the help of a local clock reference. In the past, for single chip implementations, the clock signal would be shared between the serializer 12 and the deserializer 14.
The internal frequency of the serializer 12, which must be faster than the incoming data, is set based on the compression/decompression factor of the SERDES 10. For example, a 10:1 serializer would have an internal frequency approximately 10 times the data frequency. The internal frequency of the serializer 12 is typically shared with the deserializer 14 by embedding the clock frequency into the output of the serializer.
Most newer SERDES devices accept data in any format, performing coding internally, but some older versions require input data to be pre-coded using 8b/10b coding. The 8b/10b coding scheme is based on representing each byte (8 bits) as a 10-bit code. A look-up table determines which 10-bit code corresponds to each byte. Since there are four times more 10-bit codes than 8-bit codes, the codes can be assigned so that the number of ones and zeros in the serial stream is roughly balanced. This “DC balance” is an advantage when sending data across long cables or across fiber.
Some current SERDES opt for a different scheme requiring less overhead, such as the 16/18 encoding scheme used on the DS92LV16 available from NATIONAL SEMICONDUCTOR, or the 64/66 encoding scheme defined in IEEE 802.3ae. By way of example 16/18 encoding sends a 16-bit word along with a start and stop bit for a total of 18 bits for every 16-bit word (compared to 20 bits for 8b/10b). Although not DC balanced, this scheme not only uses less overhead, but provides true live insertion capability.
The serializer 12 and deserializer 14 pair is only as good as their ability to lock onto and extract clock signals. This ability is determined, in large part, to the quality of the internal oscillators used to generate internal clock signals.
FIG. 2 is a block diagram of a phase locked loop (PLL) 30. In the serializer 12, the PLL locks to an input clock frequency and outputs a clock signal, e.g. the internal frequency, that is a multiple of the clock frequency. In the deserializer 14, a PLL is used in the clock recovery circuit to lock onto the embedded clock signal from the serializer 12.
In the generalized diagram of the PLL 30 shown in FIG. 2, a clock signal (CLOCK) is supplied to a phase detector 32 that detects a phase delta value between the CLOCK and a feedback signal. The delta is fed to a filter 34 which controls the voltage supplied to a voltage controlled oscillator (VCO) 36. In FIG. 2, the VCO 36 is shown as a ring oscillator. A ring oscillator may be coarsely tuned by switching in or out buffer stages and fine tuned using a varactor or by controlling the bias current in the buffers. A transfer function 38 sets the final ration of the CLOCK to the PLL frequency. The internal frequency of the PLL, as set by the ring oscillator 36, is responsible for timing for both serialization and clock recovery.
Most recent SERDES designs use full or partial digital PLLs to produce a locked clock signal. It has proven difficult to integrate an analog PLL into a noisy digital environment. In an all digital PLL, the phase detector is digital, such as a standard type IV detector or a bang-bang phase detector, the filter would typically comprise a counter and a digital recursive filter, and finally, the oscillator in an all-digital PLL would be a digitally controlled oscillator (DCO), such as the ring oscillator shown in FIG. 2.
From a design and power standpoint it is desirable to integrate multiple SERDES pairs onto a single chip. This requires the integration of multiple PLLs onto the same chip. As shown above, it is known to integrate ring oscillators in a SERDES. Unfortunately, ring oscillators have proven sensitive to power supply and substrate noise, which can be high in large multi-SERDES ICs. It is also known to use LC oscillators with spiral inductors. However, spiral inductors are costly in terms of space and expense making difficult to provide each SERDES with an integrated PLL. For example, spiral inductors need to be large to achieve reasonable Q factor.
It is further desirable to allocate each serializer and deserializer its own oscillator. This has proven difficult with even just a single SERDES on a chip much less with multiple SERDES on the chip, with some implementations having more than 10 SERDES pairs on a single chip. Current designs share an oscillator among several SERDES on a single IC, but such arrangements inevitably reduce flexibility of design and incur power penalties.
Accordingly, the present inventors have recognized a need for method and apparatus to integrate multiple oscillators on a multi-SERDES chip in a manner that reduces cost and facilitates a large number of SERDES pairs.